Notices by ✧✦✶✷Catherine✷✶✦✧ (whitequark@mastodon.social)

@mntmn ooooooh

@foone you could call this...

flash memory

@munin I do yeah

@foone i feel like this is a perfect application for prolog

@mntmn CP2108?

refuse the phenomenon of cutting corners

it's terrifying just how easily FPGA skills translate to Factorio circuit network skills. the main difference is that wired-AND is back with a vengeance, baby, and it's also now wired-ADD instead of wired-AND

i'll do my absolute best to never use the circuit network again

encountered the usual "too many items and not enough belts" in factorio and solved it with a bit of Verilog

always @(posedge update) begin
science_x_delta <= science_x_in + science_x_out * -1;
science_x_mem <= science_x_mem + science_x_delta;
end

i have a recurring problem where i come up with some idea for a game and then have to slap myself and go "wait. this is just reinventing my literal job again"

this is definitely one of those times.

ok so i have an incredibly cursed idea

factorio currently allows you to use only integers as values. but what if you could have higher order combinators?

"Red Science" = lambda x: x > 10

imagine how fantastically unreadable the networks would become! so much worse than the norm

KiCAD needs a PvP mode

hot take: Factorio is EDA software

i'm sorry, HDMI HEC is _what_

it is _literally Ethernet_ as in _100BASE-TX_ with very minor modifications???

"Modeline? Do you mean the Celeste girl?"

tired: GPL is not a EULA
fatigued: MIT is not a EULA

https://en.wikipedia.org/wiki/APINACA

#wikifinds

achievement unlocked: printf-debugged someone else's application that came to me as a binary (by finding a function nobody would miss, deleting it, and replacing the body with a call to printf and the first few instructions of whatever was in the place i wanted to have printed)

ISE has 30 (thirty) different "Util*" libraries. maybe more, i wouldn't count on me finding all of them

one of the 130 (one hundred thirty) shared libraries that this command loads is also patched (i've replaced 1e12 with 1e15 in the binary to adjust numeric precision of the output), and i'm trying to figure out why the patch doesn't work

you know things are going well when you're running a command that goes

$ XILINX=/opt/Xilinx/14.7/ISE_DS/ISE LD_LIBRARY_PATH=/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64 LD_PRELOAD=~/libPortability_debugStub_printf.so ~/Projects/ltrace/ltrace -e '@*Dly*' /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/netgen -sta -w ~/test.ncd

and you're not even halfway done with it