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1. polprog68k (gorplop@pleroma.m68k.church)'s status on Saturday, 21-Dec-2024 02:02:24 JST polprog68k

   • Rue Mohr
   8051 boards by @RueNahcMohr :)
   • philpem (philpem@digipres.club)'s status on Saturday, 21-Dec-2024 02:20:07 JST philpem

     in reply to

     • Rue Mohr

     @gorplop @RueNahcMohr Nice boards. I was talking to Orman about the 8051 architecture earlier. I think I called it "slow, strange, and from the same farm that gave the world x86" :D

   • polprog68k (gorplop@pleroma.m68k.church)'s status on Saturday, 21-Dec-2024 02:20:07 JST polprog68k

     in reply to

     • philpem
     • Rue Mohr
     @philpem @RueNahcMohr indeed. And these are the OG 87C51, they have no cheat switch to enable 1 clock cycle per instruction. We had a lot of the PLCC OTP variery so Rue made a basic board which grounds EA# and has an EEPROM. 8 inputs, 8 outputs, P1 exposed and thats all you really need :)
   • philpem (philpem@digipres.club)'s status on Saturday, 21-Dec-2024 02:23:04 JST philpem

     in reply to

     • Rue Mohr

     @gorplop @RueNahcMohr 1 clock per instruction! You kids and your high-speed pipelined DS89C420s! Why in my day we had the 4-clock DS87C520 and liked it!

     Sounds like a nice little setup. I used to use them where I needed a bit more than a microcontroller but didn't want to do a CPU design and all that entailed. The external bus is handy.

     polprog68k likes this.
     polprog68k repeated this.
   • Rue Mohr (ruenahcmohr@infosec.exchange)'s status on Saturday, 21-Dec-2024 04:30:26 JST Rue Mohr

     in reply to

     • philpem

     @philpem @gorplop
     I have so many chips from some recent e-waste I designed a pcb to use some up.

     https://github.com/ruenahcmohr/8051recyclerPCB

     polprogs has a version has some feature tweaks!

     polprog68k likes this.