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1. Tube🌞Time (tubetime@mastodon.social)'s status on Thursday, 28-Sep-2023 17:44:36 JST Tube🌞Time

   I'm working on a new FPGA project. this one is rather complex.

   • Tube🌞Time (tubetime@mastodon.social)'s status on Thursday, 28-Sep-2023 17:44:24 JST Tube🌞Time

     in reply to

     nice! I managed to get PIO data transfers working well enough for the buffer test routine to pass.

   • Tube🌞Time (tubetime@mastodon.social)'s status on Thursday, 28-Sep-2023 17:44:24 JST Tube🌞Time

     in reply to

     ok this is fantastic--I've managed to transfer my first actual sector! it's just using PIO and the data is not from a real filesystem, but this is another big step forward!

   • Foone🏳️‍⚧️ (foone@digipres.club)'s status on Thursday, 28-Sep-2023 17:44:24 JST Foone🏳️‍⚧️

     in reply to

     @tubetime amazing work!

   • Tube🌞Time (tubetime@mastodon.social)'s status on Thursday, 28-Sep-2023 17:44:25 JST Tube🌞Time

     in reply to

     having good test programs is important. here's the status interface register dropping values. the Teensy program is just writing an incrementing number, and the diagnostics program is checking for gaps.

   • Tube🌞Time (tubetime@mastodon.social)'s status on Thursday, 28-Sep-2023 17:44:25 JST Tube🌞Time

     in reply to

     got that all sorted out. it was a synchronization issue with the flags between the two interfaces.

     this is the "seek" command successfully completing! this is a *major* step since it requires 4 working mailboxes and interrupts.

   • Tube🌞Time (tubetime@mastodon.social)'s status on Thursday, 28-Sep-2023 17:44:25 JST Tube🌞Time

     in reply to

     another important step today--i got the data port and data port mailbox flags working. it can also detect 8-bit vs 16-bit transfers. getting very close to working PIO transfers.

   • Tube🌞Time (tubetime@mastodon.social)'s status on Thursday, 28-Sep-2023 17:44:26 JST Tube🌞Time

     in reply to

     so last night I identified the power on self test routines by inspection. it's not too hard to identify a checksum routine or a memory test routine. this helped me fill in the memory map.

     also, the POR test function stores the results at a particular memory location, and the codes match up with the POR error codes in the DBA-ESDI spec! the next step is to search the whole ROM for any instructions that read this memory location--this should identify the functions that generate the status block.

   • Tube🌞Time (tubetime@mastodon.social)'s status on Thursday, 28-Sep-2023 17:44:26 JST Tube🌞Time

     in reply to

     drive firmware is turning into a bit of a slog so i switched over to the IBM BIOS. having a spec is nice, but the code will cover a bunch of corner cases.

   • Tube🌞Time (tubetime@mastodon.social)'s status on Thursday, 28-Sep-2023 17:44:26 JST Tube🌞Time

     in reply to

     managed to reverse engineer enough that I was able to read the defect map out of one of the original hard drives. sounds easy but the process uses DMA.

   • Tube🌞Time (tubetime@mastodon.social)'s status on Thursday, 28-Sep-2023 17:44:26 JST Tube🌞Time

     in reply to

     working through a nasty timing hazard with the mailbox flags on the command port. sometimes you write data and the "data available" flag never gets set.

     so now i am digging through the logic that yosys generated to see if it even makes sense.

   • Tube🌞Time (tubetime@mastodon.social)'s status on Thursday, 28-Sep-2023 17:44:27 JST Tube🌞Time

     in reply to

     now i'm knee deep in Ghidra listings. this code probably runs the entire hard drive, not just the host interface.

   • Tube🌞Time (tubetime@mastodon.social)'s status on Thursday, 28-Sep-2023 17:44:27 JST Tube🌞Time

     in reply to

     this sort of reverse engineering is very much like solving a challenging puzzle. you push and push until you can deduce something based on what you already know, then you pivot, taking that new knowledge and pushing on that until you learn even more.

   • Tube🌞Time (tubetime@mastodon.social)'s status on Thursday, 28-Sep-2023 17:44:28 JST Tube🌞Time

     in reply to

     excellent progress today. I've been able to implement the "Get Diagnostic Status" command. it transfers the command block and handles the returning status block as well as the flags and interrupts. best of all, it works on real hardware using my diagnostic program!

   • Tube🌞Time (tubetime@mastodon.social)'s status on Thursday, 28-Sep-2023 17:44:28 JST Tube🌞Time

     in reply to

     OK why does pin 1 start halfway down the edge of this chip???

     my best guess is that the die is rotated to a 45 degree angle. anyway i want to dump the contents so i can analyze the drive firmware.

   • Tube🌞Time (tubetime@mastodon.social)'s status on Thursday, 28-Sep-2023 17:44:28 JST Tube🌞Time

     in reply to

     no 28-pin TSOP socket, oh well

   • Tube🌞Time (tubetime@mastodon.social)'s status on Thursday, 28-Sep-2023 17:44:29 JST Tube🌞Time

     in reply to

     got the Teensy interface up and running. i'm using direct IO port access on the Teensy 4.1. take a look at core_pins.h in the Teensy header files. basically you can read from GPIOx_PSR and write to GPIOx_DR.

     i also had to add a short delay to create some setup time for the FPGA--the Teensy 4.1 is a hair too fast lol

   • Tube🌞Time (tubetime@mastodon.social)'s status on Thursday, 28-Sep-2023 17:44:29 JST Tube🌞Time

     in reply to

     bidirectional registers now work! i can write a command from the PC to the Teensy, and i can write a response from the Teensy and read it from the PC. there are also status flags showing when new data is available. it may not seem like much, but this is huge progress.

   • Tube🌞Time (tubetime@mastodon.social)'s status on Thursday, 28-Sep-2023 17:44:30 JST Tube🌞Time

     in reply to

     huh, the "MADE24" line is controlled by bit 7 of register 96. I wonder what that is.

   • Tube🌞Time (tubetime@mastodon.social)'s status on Thursday, 28-Sep-2023 17:44:30 JST Tube🌞Time

     in reply to

     lol, this is the active high CHRESET! i was wondering why that line seemed to be missing.

   • Tube🌞Time (tubetime@mastodon.social)'s status on Thursday, 28-Sep-2023 17:44:30 JST Tube🌞Time

     in reply to

     moving on to the Teensy interface. i had to choose the IO pins carefully so i can make a 16-bit parallel IO port.

   • Tube🌞Time (tubetime@mastodon.social)'s status on Thursday, 28-Sep-2023 17:44:31 JST Tube🌞Time

     in reply to

     oh! now the card is putting data onto the bus! the "test1" channel is the data direction for the 74lvc4245 buffers showing that they are transferring data from the card to the host PC.

   • Tube🌞Time (tubetime@mastodon.social)'s status on Thursday, 28-Sep-2023 17:44:31 JST Tube🌞Time

     in reply to

     wow, it actually works, i'm able to write a value to the simple register and read it back. this is a HUGE step forward.

   • Tube🌞Time (tubetime@mastodon.social)'s status on Thursday, 28-Sep-2023 17:44:31 JST Tube🌞Time

     in reply to

     i'll need to figure out what is up with the MADE24 line. could be that the pin doesn't actually do that. the HDD pinout is one that i reverse engineered a while back, so it might be a mistake.

     this could also explain the damage to the PC, perhaps the card tried to write to the data bus when it was not supposed to and damaged the output drivers of some other chip.

   • Tube🌞Time (tubetime@mastodon.social)'s status on Thursday, 28-Sep-2023 17:44:32 JST Tube🌞Time

     in reply to

     hmm, so during a read operation, the data is never driven onto the bus (the output stays pulled up to FFFF). looks like the MADE24 line is staying low? that's weird. let me try making the logic ignore it.

   • Tube🌞Time (tubetime@mastodon.social)'s status on Thursday, 28-Sep-2023 17:44:33 JST Tube🌞Time

     in reply to

     the other problem (01290200) is more concerning and will need a logic analyzer.

   • Tube🌞Time (tubetime@mastodon.social)'s status on Thursday, 28-Sep-2023 17:44:33 JST Tube🌞Time

     in reply to

     yes, i made a dedicated interposer/extender board just to help with the logic analyzer connections. it's called the Fing Longer (a reference to Futurama).

   • Tube🌞Time (tubetime@mastodon.social)'s status on Thursday, 28-Sep-2023 17:44:34 JST Tube🌞Time

     in reply to

     gotta take this step by step. I should have checked this at the start but first I will force the FPGA into the unprogrammed state (-CRESET low) then check each pin to make sure it's in a valid state.

   • Tube🌞Time (tubetime@mastodon.social)'s status on Thursday, 28-Sep-2023 17:44:34 JST Tube🌞Time

     in reply to

     ok when *not* in reset, the FPGA is pulling the DMA line BURST_L low constantly. this is bad, and explains the 00011320 error i saw earlier.

   • Tube🌞Time (tubetime@mastodon.social)'s status on Thursday, 28-Sep-2023 17:44:34 JST Tube🌞Time

     in reply to

     seems that i typo'd the wiring between the top level verilog module and the module that handles the micro channel bus. it's a floating connection and it seems to mostly just sit at a logic 0.

   • Tube🌞Time (tubetime@mastodon.social)'s status on Thursday, 28-Sep-2023 17:44:35 JST Tube🌞Time

     in reply to

     wrote some temporary verilog to validate the bus interface using a single 16-bit register. here goes nothing

   • Tube🌞Time (tubetime@mastodon.social)'s status on Thursday, 28-Sep-2023 17:44:35 JST Tube🌞Time

     in reply to

     oops. logic analyzer time. guess i should have expected it.

   • Tube🌞Time (tubetime@mastodon.social)'s status on Thursday, 28-Sep-2023 17:44:35 JST Tube🌞Time

     in reply to

     ok so i unplugged the board and powered up the computer -- and the error stays. looks like i broke something. 😩

   • Tube🌞Time (tubetime@mastodon.social)'s status on Thursday, 28-Sep-2023 17:44:36 JST Tube🌞Time

     in reply to

     I'm at the "blink an LED" stage of bringing it up.