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1. enzymical (e@ryona.agency)'s status on Thursday, 24-Aug-2023 22:27:40 JST enzymical
   its unreal how long Intel and AMD took to provide the user with a proper unified memory copy/fill instruction(rep movs/rep stos)
   with the Pentium it was slow as hell
   then they improved it with "Fast Strings" for data larger than 256 bytes, still with a 36-cycle startup cost
   then they finally implemented "Fast Short REP MOVS" and "Fast Short REP STOS" in Ice Lake(2019) but it still loses out to nontemporal MOVNTDQ+PREFETCHNTA loops which are barely able to overwhelm the memory bus speed
   :niggainsane:
   • :blank: (i@declin.eu)'s status on Thursday, 24-Aug-2023 22:27:37 JST :blank:

     in reply to

     • Rusty Crab
     • paula
     @paula @RustyCrab @e
     Machismo repeated this.
   • paula (paula@marsey.moe)'s status on Thursday, 24-Aug-2023 22:27:38 JST paula

     in reply to

     • Rusty Crab
     is there an image like this but for intel/arm asm instructions?
     Machismo repeated this.
   • Rusty Crab (rustycrab@clubcyberia.co)'s status on Thursday, 24-Aug-2023 22:27:39 JST Rusty Crab

     in reply to
     @e
     >MOVNTDQ+PREFETCHNTA
     oh great what are the new pronouns
   • enzymical (e@ryona.agency)'s status on Thursday, 24-Aug-2023 22:27:39 JST enzymical

     in reply to

     • Rusty Crab
     @RustyCrab my pronouns are VPSHUFBITQMB/VFMADDSUB213PH/GF2P8AFFINEINVQB, thank you
   • PC-9801 Enjoyer (pawlicker@bae.st)'s status on Thursday, 24-Aug-2023 22:28:27 JST PC-9801 Enjoyer

     in reply to

     • :blank:
     • Rusty Crab
     • paula
     @i @RustyCrab @paula @e you should have referenced this and how risc cpus lacked multiply and divide instructions
     https://docs.oracle.com/cd/E19120-01/open.solaris/819-3196/hwovr-165/index.html