Conversation

Notices

1. Adrian Cochrane (alcinnz@floss.social)'s status on Thursday, 09-Mar-2023 04:02:09 JST Adrian Cochrane

   Inside the 8086 processor's instruction prefetch circuitry - Ken Shirriff: http://www.righto.com/2023/01/inside-8086-processors-instruction.html

   • Vertigo #$FF (vertigo@hackers.town)'s status on Thursday, 09-Mar-2023 04:16:42 JST Vertigo #$FF

     in reply to

     @alcinnz Without a cache, there's no need for data prefetch. If you could support the CPU's instruction fetch rate at full speed, you automatically could handle data access at maximum speed already.

   • Adrian Cochrane (alcinnz@floss.social)'s status on Thursday, 09-Mar-2023 04:18:29 JST Adrian Cochrane

     in reply to

     • Vertigo #$FF

     @vertigo I do read that there were memcpy back then, but they were part of the GPU for computers which had ones.

   • Vertigo #$FF (vertigo@hackers.town)'s status on Thursday, 09-Mar-2023 04:59:58 JST Vertigo #$FF

     in reply to

     @alcinnz On the Z80, you had the LDIR and LDDR instructions to memcpy; on 8086, REP MOVSW.

     The 68010 introduced "loop mode", so you could do the same with:

     LP: move.w (a0)+,(a1)+
     dbne d0,LP
     

     with comparable performance.