Conversation

Notices

1. minute (mntmn@mastodon.social)'s status on Tuesday, 31-Jan-2023 22:07:07 JST minute

   a brace to keep that clock away (workaround for display SI issue with RKX7 fpga module)

   • minute (mntmn@mastodon.social)'s status on Tuesday, 31-Jan-2023 22:16:10 JST minute

     in reply to

     • srslypascal

     @srslypascal yep, missing GND lines between the clock and the rest was the mistake here, but can't respin these now.

   • srslypascal (srslypascal@chaos.social)'s status on Tuesday, 31-Jan-2023 22:16:11 JST srslypascal

     in reply to

     @mntmn
     Up next: triple-layer FFC with an additional ground trace on either side of the clock traces 🥳

   • minute (mntmn@mastodon.social)'s status on Tuesday, 31-Jan-2023 22:16:35 JST minute

     in reply to

     • Wolf480pl

     @wolf480pl yeah, the pixel clock would cause distortions if it was too close

   • Wolf480pl (wolf480pl@mstdn.io)'s status on Tuesday, 31-Jan-2023 22:16:36 JST Wolf480pl

     in reply to

     @mntmn lol

     was the clock interfering with the other lines?

   • minute (mntmn@mastodon.social)'s status on Tuesday, 31-Jan-2023 22:16:51 JST minute

     in reply to

     • Wolf480pl

     @wolf480pl (it's a parallel rgb bus for HD display)

   • minute (mntmn@mastodon.social)'s status on Tuesday, 31-Jan-2023 22:40:51 JST minute

     in reply to

     • Wolf480pl

     @wolf480pl the parallel to serial (displayport) converter chip is on that separate little pcb. it is so that you have flexible choice of what to connect to the FPGA IOs.

   • Wolf480pl (wolf480pl@mstdn.io)'s status on Tuesday, 31-Jan-2023 22:40:53 JST Wolf480pl

     in reply to

     @mntmn is it parallel so that the FPGA can keep up, or is it the display that requires parallel?

     Also, is my intuition wrong that a serial link would be more interference-resistant because it'd go over differential pairs and you'd have lots of free pins to put ground on both sides of it?