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1. minute (mntmn@mastodon.social)'s status on Wednesday, 11-Oct-2023 23:42:44 JST minute

   i have a bizarre yield issue with some of our custom produced LS1028A SOMs, maybe 30% are like that. the processor will not start up correctly: it does not try to talk to SD card (no clock), and it's H_RESET output does not go high. resetting it with PORESET doesn't help. but turning it off and on again eventually makes it boot, and it's then stable even through many PORESETs. it is not predictable (so far) when/what makes it boot, so far it looks random. who can i pay to debug this?

   • minute (mntmn@mastodon.social)'s status on Wednesday, 11-Oct-2023 23:44:13 JST minute

     in reply to

     it might be that something is visible on JTAG, i haven't tried that yet (it requires wiring ob some test points to codewarrior TAP)

   • minute (mntmn@mastodon.social)'s status on Wednesday, 11-Oct-2023 23:50:44 JST minute

     in reply to

     i can't afford to spend many days or weeks on this because we have too many other pressing projects and shipments to do, so in the worst case we have to throw 30-40% of the batch away (which is yet to be fully produced) or store them until later if someone becomes available who has the skills and equipment to debug this.

   • minute (mntmn@mastodon.social)'s status on Wednesday, 11-Oct-2023 23:52:49 JST minute

     in reply to

     while debugging i also developed an experimental firmware for the motherboard LPC that automates the turning-it-off-and-on-again and checks the HRESET line after one second to determine if it has booted, and it just cycles until it boots. but this doesn't work on all modules... because especially strange is that the H_RESET level can behave differently.

   • minute (mntmn@mastodon.social)'s status on Wednesday, 11-Oct-2023 23:53:59 JST minute

     in reply to

     it's a bit like those old lawnmowers where you had to pull the cord many times to start the motor.

   • Paul Targosz 🦦 (sickeroni@mastodon.social)'s status on Wednesday, 11-Oct-2023 23:56:10 JST Paul Targosz 🦦

     in reply to

     @mntmn sounds strongly like a dangling pin. (and only saturated after some special cases/over time) If there are not to many to test, pull every pin up and down. It also feels like a boot configuration config based on that pin... that could be checked, also (datasheet & your idea with jtag)
     short: check your gpios used for boot up flags.. (even just using osciloscope probs can already help)

   • minute (mntmn@mastodon.social)'s status on Wednesday, 11-Oct-2023 23:57:56 JST minute

     in reply to

     • Graham Sutherland / Polynomial

     @gsuberland ah lol!

   • Graham Sutherland / Polynomial (gsuberland@chaos.social)'s status on Wednesday, 11-Oct-2023 23:57:57 JST Graham Sutherland / Polynomial

     in reply to

     @mntmn "old" lol they still do that today

   • minute (mntmn@mastodon.social)'s status on Wednesday, 11-Oct-2023 23:58:34 JST minute

     in reply to

     • Paul Targosz 🦦

     @sickeroni yeah, these are already checked and also all (i think) voltage rails

   • abortretryfail (abortretryfail@mastodon.social)'s status on Thursday, 12-Oct-2023 00:06:28 JST abortretryfail

     in reply to

     @mntmn What's the supply voltages look like when that thing powers up? 🤔

   • minute (mntmn@mastodon.social)'s status on Thursday, 12-Oct-2023 00:19:01 JST minute

     in reply to

     • abortretryfail
     • talpa

     @talpa @abortretryfail

   • talpa (talpa@fosstodon.org)'s status on Thursday, 12-Oct-2023 00:19:02 JST talpa

     in reply to

     • abortretryfail

     @abortretryfail @mntmn I was wondering if the module required some sort of power sequencing, and if the timing was marginal.

   • minute (mntmn@mastodon.social)'s status on Thursday, 12-Oct-2023 00:26:49 JST minute

     in reply to

     • Adam ♿

     @voltagex i'll try, but it wasn't easy or helpful to get support there in the past

   • Adam ♿ (voltagex@aus.social)'s status on Thursday, 12-Oct-2023 00:26:50 JST Adam ♿

     in reply to

     @mntmn NXP won't help?

   • minute (mntmn@mastodon.social)'s status on Thursday, 12-Oct-2023 00:33:34 JST minute

     in reply to

     • Kevin Marks

     @KevinMarks not sure if i understand

   • Kevin Marks (kevinmarks@xoxo.zone)'s status on Thursday, 12-Oct-2023 00:33:36 JST Kevin Marks

     in reply to

     @mntmn is there part of the startup routine that assumes that buffers are full of zeros, and if they're full of noise instead could be misinterpreting contents as signal?

   • minute (mntmn@mastodon.social)'s status on Thursday, 12-Oct-2023 00:54:00 JST minute

     in reply to

     • Dirk Eibach

     @de ok!

   • Dirk Eibach (de@noc.social)'s status on Thursday, 12-Oct-2023 00:54:03 JST Dirk Eibach

     in reply to

     @mntmn Just throw one of the non-working into my package and I will give it a try,
     😉

   • minute (mntmn@mastodon.social)'s status on Thursday, 12-Oct-2023 02:10:06 JST minute

     in reply to

     • F4GRX Sébastien
     • abortretryfail
     • talpa

     @f4grx @talpa @abortretryfail i think that's just some nonsense

   • F4GRX Sébastien (f4grx@chaos.social)'s status on Thursday, 12-Oct-2023 02:10:07 JST F4GRX Sébastien

     in reply to

     • abortretryfail
     • talpa

     @mntmn @talpa @abortretryfail only 300000 POR allowed? The device writes to flash/eeprom each time it boots?

   • minute (mntmn@mastodon.social)'s status on Thursday, 12-Oct-2023 02:55:20 JST minute

     in reply to

     • abortretryfail
     • talpa

     @talpa @abortretryfail confirmed, it is as you say, TA_BB_VDD is good 1.5ms before VDD has ramped up.

   • talpa (talpa@fosstodon.org)'s status on Thursday, 12-Oct-2023 02:55:21 JST talpa

     in reply to

     • abortretryfail

     @mntmn @abortretryfail I would consider double checking that TA_BB_VDD is good before VDD.
     I'm not having high hopes though, it is powered from 3V3 which is PG before 1V35 and then VDD.
     Also with a 100k mode VDD should take ages to soft start (1.4ms) and the lin reg only takes 0.1ms and has a head start

   • minute (mntmn@mastodon.social)'s status on Thursday, 12-Oct-2023 03:11:00 JST minute

     in reply to

     • abortretryfail
     • talpa

     @talpa @abortretryfail what kind of pF do you suggest?

   • talpa (talpa@fosstodon.org)'s status on Thursday, 12-Oct-2023 03:11:01 JST talpa

     in reply to

     • abortretryfail

     @mntmn @abortretryfail Maybe also trying to add a high frequency cap on the VDD regulator input (solder it on top one of the bulk ones) even though data sheet doesn't use one...

     Also you probably would have notices noise on the 5V line when you probed it (and why only during startup?)

   • Yann Sionneau (yannsionneau@mastodon.online)'s status on Friday, 13-Oct-2023 19:16:46 JST Yann Sionneau

     in reply to

     @mntmn I've ping'ed a friend of mine who's working as independent electronic engineer in a cooperative, but not sure if he has time ^^

   • minute (mntmn@mastodon.social)'s status on Friday, 13-Oct-2023 19:16:46 JST minute

     in reply to

     • Yann Sionneau

     @yannsionneau thanks in any case!