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1. Foone🏳️‍⚧️ (foone@digipres.club)'s status on Sunday, 08-Oct-2023 02:25:22 JST Foone🏳️‍⚧️

   To compete with RISC-V I'm going to design my own ISA and call it CISC-VI

   What now?

   • Foone🏳️‍⚧️ (foone@digipres.club)'s status on Sunday, 08-Oct-2023 02:35:17 JST Foone🏳️‍⚧️

     in reply to

     No microcode and no instructions. Super long instruction word:
     Every bit in the instruction corresponds to a single control line in the processor.

     So yeah. Instructions are 327 bits long

   • Foone🏳️‍⚧️ (foone@digipres.club)'s status on Sunday, 08-Oct-2023 02:43:09 JST Foone🏳️‍⚧️

     in reply to

     • illegally Rylie 🏳️‍⚧️✨

     @Specialist_Being_677 transc-LXIX!

   • illegally Rylie 🏳️‍⚧️✨ (specialist_being_677@hachyderm.io)'s status on Sunday, 08-Oct-2023 02:43:10 JST illegally Rylie 🏳️‍⚧️✨

     in reply to

     @foone that is nearly impossible to say. Also too cis 😅

   • Foone🏳️‍⚧️ (foone@digipres.club)'s status on Sunday, 08-Oct-2023 02:47:27 JST Foone🏳️‍⚧️

     in reply to

     • Brian Danger Hicks

     @ckape well we can't exactly add more control lines at runtime!

   • Brian Danger Hicks (ckape@teh.entar.net)'s status on Sunday, 08-Oct-2023 02:47:28 JST Brian Danger Hicks

     in reply to

     @foone A constant instruction length seems like it would get too constraining