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1. not good psdev 🏳️‍⚧️ (mothcompute@vixen.zone)'s status on Thursday, 19-Dec-2024 06:15:33 JST not good psdev 🏳️‍⚧️

   mathematics is like computers in a beautiful world where there is no such thing as a clock cycle

   • polprog68k likes this.
   • polprog68k (gorplop@pleroma.m68k.church)'s status on Thursday, 19-Dec-2024 06:19:06 JST polprog68k

     in reply to
     @mothcompute vector compare sign extended bcd immediate with indirect branch
   • not good psdev 🏳️‍⚧️ (mothcompute@vixen.zone)'s status on Thursday, 19-Dec-2024 06:19:07 JST not good psdev 🏳️‍⚧️

     in reply to

     i need scary looking ultra cisc summation operators like they have on weird billion dollar mainframes

   • polprog68k (gorplop@pleroma.m68k.church)'s status on Thursday, 19-Dec-2024 06:24:16 JST polprog68k

     in reply to

     • polprog68k
     @mothcompute everytime I need a laugh i open https://publibfp.dhe.ibm.com/epubs/pdf/a227832c.pdf and look at the instruction set summary
   • polprog68k (gorplop@pleroma.m68k.church)'s status on Thursday, 19-Dec-2024 07:11:26 JST polprog68k

     in reply to
     @mothcompute we should get ome of these HP NICs with Altera FPGAs on them and make a UTF converter coprocessor
   • not good psdev 🏳️‍⚧️ (mothcompute@vixen.zone)'s status on Thursday, 19-Dec-2024 07:11:27 JST not good psdev 🏳️‍⚧️

     in reply to

     • polprog68k

     @gorplop x86 needs this

     polprog68k likes this.