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1. Foone🏳️‍⚧️ (foone@digipres.club)'s status on Friday, 09-Aug-2024 05:51:08 JST Foone🏳️‍⚧️

   That new pico is neat. A chip that can change architectures? And even, technically, run as two heterogeneous cores?

   Neat! Can you add x86 to the pico3? Thanks.

   • Foone🏳️‍⚧️ (foone@digipres.club)'s status on Friday, 09-Aug-2024 05:53:07 JST Foone🏳️‍⚧️

     in reply to

     I do really like the idea of a chip that boots up, checks to see what CPU architecture its flash code is in, then reboots to support that architecture instead

   • Foone🏳️‍⚧️ (foone@digipres.club)'s status on Friday, 09-Aug-2024 05:54:18 JST Foone🏳️‍⚧️

     in reply to

     Like I'm imagining sticking an 80486 in a Mac and it notices the firmware is powerpc so it reboots into being a powerpc chip

   • Foone🏳️‍⚧️ (foone@digipres.club)'s status on Friday, 09-Aug-2024 06:11:16 JST Foone🏳️‍⚧️

     in reply to

     • HawkWolf (H. A. Kirsch)

     @hakirsch nah! They're not doing code morphing or anything: the chip has four cores (two of each arch) and at boot it picks which two to turn on

   • HawkWolf (H. A. Kirsch) (hakirsch@furries.club)'s status on Friday, 09-Aug-2024 06:11:17 JST HawkWolf (H. A. Kirsch)

     in reply to

     @foone isn't this slightly kind of but not really like the Transmeta Crusoe?

   • Foone🏳️‍⚧️ (foone@digipres.club)'s status on Friday, 09-Aug-2024 06:57:45 JST Foone🏳️‍⚧️

     in reply to

     • Ted Mielczarek

     @tedmielczarek nope! defunct since 2009

   • Ted Mielczarek (tedmielczarek@mastodon.social)'s status on Friday, 09-Aug-2024 06:57:46 JST Ted Mielczarek

     in reply to

     @foone is transmeta still a thing?

   • Foone🏳️‍⚧️ (foone@digipres.club)'s status on Friday, 09-Aug-2024 06:59:30 JST Foone🏳️‍⚧️

     in reply to

     to explain something for anyone who hasn't read the RP2350 datasheet:

     It doesn't do any code-morphing or translation or anything. The CPU is designed with 4 cores, but two slots for connecting to the rest of the CPU fabric.

     So at boot it selects which two cores to power on. So it can be 2xARM or 2xRISCV or (technically!) 1xARM and 1xRISCV. There's no fancy stuff where there's a single CPU arch that can run multiple things: it's just multiple heterogynous cores.

   • Foone🏳️‍⚧️ (foone@digipres.club)'s status on Friday, 09-Aug-2024 08:08:26 JST Foone🏳️‍⚧️

     in reply to

     • LovesTha🥧
     • Pete Keen

     @LovesTha @zrail I don't think so. I think you set the arch bits to select which cores you want, and then reboot the whole CPU

   • Pete Keen (zrail@hachyderm.io)'s status on Friday, 09-Aug-2024 08:08:27 JST Pete Keen

     in reply to

     @foone not just at boot! Boot selects core 0 but you can pick what arch to start for core 1 at runtime. You have to ship two binaries of course, and it seems like the tooling isn't quite there yet. But it's possible.

   • LovesTha🥧 (lovestha@floss.social)'s status on Friday, 09-Aug-2024 08:08:27 JST LovesTha🥧

     in reply to

     • Pete Keen

     @zrail @foone can core 1 be rebooted into the other arch while keeping core 0 running? (not something I'd normally expect to work, but this sounds like a device that might want to be able to do that)