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1. minute (mntmn@mastodon.social)'s status on Sunday, 09-Jun-2024 07:26:21 JST minute

   in reply to

   • Kristin Davidson {kxd}

   @aphistic hmm, to try to come up with something helpful i'd need to know a bit more about the goals and which abstraction level your implementation is on. do you want to implement a pcie root controller or device in an fpga? do you want to write a driver for pcie ip in a soc? or do you want to know how to make a schematic and layout for a pcie slot/connection between a soc or bridge and a device?

   • Kristin Davidson {kxd} (aphistic@advent.social)'s status on Sunday, 09-Jun-2024 07:26:40 JST Kristin Davidson {kxd}

     in reply to

     @mntmn Hmm, looking at it some more it seems like the part that I should be looking at is the SoM. It seems like the PCIe implementation is in the SoC, so I'd probably want to start there?

   • Kristin Davidson {kxd} (aphistic@advent.social)'s status on Sunday, 09-Jun-2024 07:26:41 JST Kristin Davidson {kxd}

     @mntmn Do you have any recommendations on places to learn about designing a system with a PCIe bus and NVMe?
     I don't even know where I'd start, but I have a project in mind I'd like to use those in. It would be an embedded device, not a PC, so I don't think it would need everything the Reform has? I was looking at the Reform schematics, but thought there might be a higher-level place to start?