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1. Ken Shirriff (kenshirriff@oldbytes.space)'s status on Wednesday, 22-Feb-2023 16:10:28 JST Ken Shirriff

   The iconic Intel 8086 processor (1978) set the path for modern computers. Like most CPUs, it supports interrupts, a mechanism to interrupt the regular flow of processing. I've been reverse-engineering it from the silicon die, and I can explain how its interrupt circuitry works.

   • Adrian Cochrane repeated this.
   • Ken Shirriff (kenshirriff@oldbytes.space)'s status on Wednesday, 22-Feb-2023 16:11:15 JST Ken Shirriff

     in reply to

     The interrupt circuitry is implemented both in microcode and hardware. Microcode is a layer between machine instructions and the hardware, executing low-level 21-bit micro-instructions. These perform moves, combined with several types of actions: ALU, memory, jumps, etc.

     Adrian Cochrane repeated this.
   • Ken Shirriff (kenshirriff@oldbytes.space)'s status on Wednesday, 22-Feb-2023 16:11:24 JST Ken Shirriff

     in reply to

     The 8086 chip supports 256 different interrupts. Each one has an entry in a "vector table" pointing to the code that handles that interrupt. The microcode gets the right address from the vector table and does a subroutine call to that handler routine.

     Adrian Cochrane repeated this.
   • Ken Shirriff (kenshirriff@oldbytes.space)'s status on Wednesday, 22-Feb-2023 16:11:30 JST Ken Shirriff

     in reply to

     For a software interrupt, this INTR microcode pushes the flags and gets the interrupt handler address from the vector table. Two adds multiply the interrupt number by 4 to get the table address. The FARCALL2 and NEARCALL routines do a subroutine call to the handler.

     Adrian Cochrane repeated this.
   • Ken Shirriff (kenshirriff@oldbytes.space)'s status on Wednesday, 22-Feb-2023 16:11:38 JST Ken Shirriff

     in reply to

     The external interrupt pins each have a circuit to clean up the interrupt signal and synchronize it to the 8086's clock. An input protection diode, inverters, and a two-stage latch. "Superbuffers" built from two transistors provide more current than regular NMOS buffers.

     Adrian Cochrane repeated this.
   • Ken Shirriff (kenshirriff@oldbytes.space)'s status on Wednesday, 22-Feb-2023 16:11:43 JST Ken Shirriff

     in reply to

     From there, external interrupts go to some logic that prioritizes the interrupts, decides when the system can handle them (usually at the end of an instruction), and signals the microcode to execute the appropriate interrupt code.

     Adrian Cochrane repeated this.
   • Ken Shirriff (kenshirriff@oldbytes.space)'s status on Wednesday, 22-Feb-2023 16:11:48 JST Ken Shirriff

     in reply to

     The INTR pin triggers a complicated interrupt that runs INTA two bus cycles to acknowledge the interrupt (for historical reasons from the 8008 and 8080 processors). The interrupt bus cycle is similar to a memory read but gets an interrupt type value from the external device.

   • Ken Shirriff (kenshirriff@oldbytes.space)'s status on Wednesday, 22-Feb-2023 16:11:56 JST Ken Shirriff

     in reply to

     For lots more details and a microcode walkthrough, see my latest blog post: https://www.righto.com/2023/02/8086-interrupt.html